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Timing constraints are used to specify the timing characteristics of the design. Timing constraints may affect all internal timing interconnections, delays through logic and LUTs and between flip-flops or registers. Timing constraints can be either global or path-specific.Explore
VHDL for Simulation
Understand the VHDL Simulation Concept. Learn how to setup your Test Bench and apply different types of Stimuli to verify your design.Explore
Verilog for Simulation
Understand the Verilog Simulation Concept. Learn how to setup your Test Fixture and apply different types of Stimuli to verify your design.Explore
Understand the meta stability problem and learn which synchronization technique should be used to design reliable clock domain crossing path.Explore