Stay up-to-date! News from LEC2

The Lattice Education Competence Center is your platform around Low-Power FPGAs. Stay up-to-date with all the latest developments.

Stay up-to-date! News from LEC2

Get the latest news from LEC2!

Latest Training Modules Available

Timing Constraints

Timing constraints are used to specify the timing characteristics of the design. Timing constraints may affect all internal timing interconnections, delays through logic and LUTs and between flip-flops or registers. Timing constraints can be either global or path-specific.

Explore

VHDL for Simulation

Understand the VHDL Simulation Concept. Learn how to setup your Test Bench and apply different types of Stimuli to verify your design.

Explore

Verilog for Simulation

Understand the Verilog Simulation Concept. Learn how to setup your Test Fixture and apply different types of Stimuli to verify your design.

Explore

CDC

Understand the meta stability problem and learn which synchronization technique should be used to design reliable clock domain crossing path.

Explore

Invest in the future and start your FPGA journey with us!

We give you the knowledge and are committed to innovate. We have the key solutions and are providing you with all the tools necessary in this constantly evolving and future oriented industry.

 

Loading