The phenomenon of metastability is inherent in clocked digital logic. Every bistable device will have two stable states and also a third metastable state. If the device enters its metastable state, it will stay there for an indeterminate and unbounded length of time before eventually transitioning into one of the stable states.
All registers in digital devices such as FPGAs have defined signal timing requirements that allow each register to correctly capture data at its inputs and produce an output signal. To ensure reliable operation, the input to a register must be stable for a minimum time before the clock edge (register setup time) and for a minimum time after the clock edge (register hold time). The register output then is available after a specified clock-to-output delay.
Metastability problems commonly occur when a signal is transferred between circuitry in unrelated or asynchronous clock domains. The designer cannot guarantee that the signal will meet register setup and hold time requirements in this case, because the signal can arrive at any time relative to the destination clock.
Physics dictates that you cannot eliminate metastability. However, you can minimize its effects and reduce the probability of failure by isolating the asynchronous inputs using a synchronizer circuit. The synchronizer conditions the input into a known relationship with the system clock.
Therefore, for the successful implementation of digital circuits in the FPGA, the strong knowledge of metastability and basic synchronization techniques is mandatory.