CDC

CDC

The phenomenon of metastability is inherent in clocked digital logic. Every bistable device will have two stable states and also a third metastable state. If the device enters its metastable state, it will stay there for an indeterminate and unbounded length of time before eventually transitioning into one of the stable states.

All registers in digital devices such as FPGAs have defined signal timing requirements that allow each register to correctly capture data at its inputs and produce an output signal. To ensure reliable operation, the input to a register must be stable for a minimum time before the clock edge (register setup time) and for a minimum time after the clock edge (register hold time). The register output then is available after a specified clock-to-output delay.

Metastability problems commonly occur when a signal is transferred between circuitry in unrelated or asynchronous clock domains. The designer cannot guarantee that the signal will meet register setup and hold time requirements in this case, because the signal can arrive at any time relative to the destination clock.

Physics dictates that you cannot eliminate metastability. However, you can minimize its effects and reduce the probability of failure by isolating the asynchronous inputs using a synchronizer circuit. The synchronizer conditions the input into a known relationship with the system clock.

Therefore, for the successful implementation of digital circuits in the FPGA, the strong knowledge of metastability and basic synchronization techniques is mandatory.

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Face2Face

Face2Face

Online

Online

Shorties

Shorties

Webinar

Webinar
Type Of Training:
Face2Face
Execution of Training:
Live Course
Cost:
2.100,00  + tax
Date:
No date provided yet
Duration:
3 full days
Location:
Online
Participant Documents Provided:
Work Book with all presentations. Lab Book to be used for exercises.
Course Objectives:
  • Introduction to metastability
  • Introduction to synchronization techniques
  • Definition of synchronization Circuits
  • Definition of Timing Constraints for CDC
Type Of Training:
Online
Execution of Training:
Live Course
Cost:
1.800,00  + tax
Date:
No date provided yet
Duration:
3 days with 4 hours per day
Location:
Online
Participant Documents Provided:
Work Book with all presentations. Lab Book to be used for exercises.
Course Objectives:
  • Introduction to metastability
  • Introduction to synchronization techniques
  • Definition of synchronization Circuits
  • Definition of Timing Constraints for CDC
Type Of Training:
Shorties
Execution of Training:
Live Course
Cost:
99,00  + tax
Date:
No date provided yet
Duration:
4 hours
Location:
Online
Participant Documents Provided:
Work Book with all presentations. Lab Book to be used for exercises.
Course Objectives:
  • Introduction to metastability
  • Introduction to synchronization techniques
  • Definition of synchronization Circuits
  • Definition of Timing Constraints for CDC
Type Of Training:
Webinar
Execution of Training:
Cost:
0,00  + tax
Date:
No date provided yet
Duration:
1 hour
Location:
Online
Participant Documents Provided:
Course Objectives:
  • Introduction to metastability
  • Introduction to synchronization techniques
  • Definition of synchronization Circuits
  • Definition of Timing Constraints for CDC

A basic knowledge in digital circuit design (gates, multiplexers, flip-flops, memories), are welcome. The theoretical content is supplemented by exercises presented by the trainer and carried out by the participant.

1. VHDL Concept and Design Units

1.1. Design Paradigm

1.2. Libraries and compiled units

1.3. Packages

1.4. Entity

1.5. Architecture

1.6. Configuration

1.7. Test Bench and Simulation

2. Data Types

2.1. Scalar

2.2. Complex Types

2.3. Sub Types and Aliases

2.4. Attributes

3. Naming Conventions and Declarations

4. Statements and Assignments

5. Sequential Statements

5.1. Statements

5.2. Sub Programs

6. Signals

6.1. Declaration

6.2. Signal Assignments inside Processes

6.3. Implicitly Signal Type Resolution and Bus Driver

6.4. Attributes

7. Concurrent Statements

8. Structural Descriptions

8.1. Hierarchical Descriptions

8.2. Use of Packages

8.3. Configurations

8.4. Generics

8.5. Structural Statements

9. Libraries and Packages

9.1. Packages

9.1.1. STD_LOGIC_1164

9.1.2. Unsigned

9.1.3. Fixed Point Package 

9.1.4. Floating Point Package

9.2. Libraries

10. Test Bench

10.1. Introduction to Test Benches

10.2. Types of Test Benches

10.3. Example

11. Labs

11.1. Simple Counter

11.2. Finite State Machines

11.3. UART

11.4. Fixed Point / Floating Point Arithmetic

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