Device Architecture to enable vision implementations

Device Architecture to enable vision implementations

Lattice device architecture integrates primitives that allow you to optimize performance and get an easier implementation of high-speed Video protocols.

This Webinar will highlight the design challenges associated with high-speed video interfaces (e.g.: MIPI, DDR, LVDS, HDMI, …) and the architectural elements that make this implementation more predictable and easier to use.

We will discuss source-synchronous interfaces as well as SERDES based interfaces and provide examples of Lattice software IP configuration tools to implement these interfaces. A guideline about the best devices to use for each protocol will be discussed.

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Webinar

Webinar
Type Of Training:
Webinar
Execution of Training:
Cost:
0,00  + tax
Date:
No date provided yet
Duration:
1 hour
Location:
Online
Participant Documents Provided:
Course Objectives:

The objective of this course is to provide an overview of the challenges that engineers will meet while implementing some Vision protocols. We will have a quick overview of source-synchronous protocols ( MIPI-CSI, DDR memory interface, …) and SERDES based protocols (SLVS-EC, …). Our goal is to highlight the architecture element of Lattice technology that will allow you to save time, have an efficient implementation and meet the performance required for each standard.

 

Vision-related solutions by example

  • Image sensor bridging/aggregation
  • Display interface
  • Heterogenous sensor aggregation

High-speed interface challenges

Source synchronous interfaces implementation

  • External interface types (SDR, DDR)
  • Data & Clock Skew
  • FPGA Programmable I/O cell Architecture
  • DDR Memory & MIPI CSI sensor interface details
  • Software tools & IP configuration
  • Supported protocol by device summary

SERDES Based protocols

  • SERDES Link and Flexible PCS (Physical coding sublayer) architecture
  • SLVS-EC architecture and IP configuration
  • Supported protocol by device summary

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