FPGA Design Technique

FPGA Design Technique

For the successful implementation of digital circuits in the FPGA, the strong knowledge of the digital circuit’s basics is mandatory. The HDL based developing method simplifies the developing cycle, but for that, the developer must have the good knowledge of digital circuit design. Although most of the developers basically know the digital components like combinational and sequential and their usage, it is very important to know the FPGA architecture for which a digital design should be implemented.

After the review of combinational and sequential circuits, the design of combinatorial circuits, sequential circuits and sequential systems will be discussed.

In almost every digital design there is Clock Domain Crossing where CDC Analysis and synchronization circuits are needed, which is described. Finally, Timing Constraints and Timing Analysis is discussed.

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Webinar

Webinar
Type Of Training:
Webinar
Execution of Training:
Live Course
Cost:
0,00  + tax
Date:
No date provided yet
Duration:
1 hour
Location:
Online
Participant Documents Provided:
Work Book with all presentations. Lab Book to be used for exercises.
Course Objectives:
  • Describe the internal structures of FPGAs
  • Describe the clocking structures of FPGAs
  • Understand synchronous design techniques
  • Understand Clock Domain Crossing
  • Describe synchronization Circuits
  • Understand Timing Constraints and Timing Analysis

A basic knowledge in digital circuit design (gates, multiplexers, flip-flops, memories), are welcome. The theoretical content is supplemented by exercises presented by the trainer and carried out by the participant.

1. VHDL Concept and Design Units

1.1. Design Paradigm

1.2. Libraries and compiled units

1.3. Packages

1.4. Entity

1.5. Architecture

1.6. Configuration

1.7. Test Bench and Simulation

2. Data Types

2.1. Scalar

2.2. Complex Types

2.3. Sub Types and Aliases

2.4. Attributes

3. Naming Conventions and Declarations

4. Statements and Assignments

5. Sequential Statements

5.1. Statements

5.2. Sub Programs

6. Signals

6.1. Declaration

6.2. Signal Assignments inside Processes

6.3. Implicitly Signal Type Resolution and Bus Driver

6.4. Attributes

7. Concurrent Statements

8. Structural Descriptions

8.1. Hierarchical Descriptions

8.2. Use of Packages

8.3. Configurations

8.4. Generics

8.5. Structural Statements

9. Libraries and Packages

9.1. Packages

9.1.1. STD_LOGIC_1164

9.1.2. Unsigned

9.1.3. Fixed Point Package 

9.1.4. Floating Point Package

9.2. Libraries

10. Test Bench

10.1. Introduction to Test Benches

10.2. Types of Test Benches

10.3. Example

11. Labs

11.1. Simple Counter

11.2. Finite State Machines

11.3. UART

11.4. Fixed Point / Floating Point Arithmetic

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