ModelSim Lattice Edition
As FPGA designs become more and more complex, the challenges to create error-free designs increase enormously. Long gone are the days of simply implementing some functionality, testing it in hardware and then iteratively improving it.
Today’s designs require a structured development process and sophisticated verification strategies. Simulation, be it behavioural, RTL or gate-level is an important part of the overall FPGA design flow.
A simple simulation environment can be set up in little time but makes debugging your design a lot easier and more efficient. With the implemented functionality and the interfaces becoming more complex the verification environment will grow as well.