Verilog for Simulation

Verilog for Simulation

Verilog Hardware Description Language offers a powerful concept which prohibits typical programming mistakes in the coding phase. Usually, Verilog is used on the register transfer level (RTL) to design digital circuits of any complexity.

Apart from the language constructs for synthesis, Verilog offers a wide range of functionality to describe complex verification models. thus, it is possible verify digital designs from simple gate up to complicated System-on-Chip (SoC) before going to lab tests.

With recourse to already well-known Verilog Language features, this workshop will deepen the knowledge in Verilog and enable the attendee to create simulations with the Verilog testbench concept. The theoretical knowledge will be deepened with selected examples and labs on PC.

A basic knowledge in the Verilog hardware description language, e.g. from Workshop “Intensive Verilog for Synthesis” is desirable. The theoretical content is supplemented by exercises carried out by the participant.

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Face2Face

Face2Face

Online

Online

Shorties

Shorties

Webinar

Webinar
Type Of Training:
Face2Face
Execution of Training:
Live Course
Cost:
2100 $ (+ tax)
Date:
Duration:
3 full days
Location:
Online
Participant Documents Provided:
Work Book with all presentations. Lab Book to be used for exercises.
Course Objectives:
  • Re-visit the basic Verilog Concept
  • Define Verilog Test Fixtures
  • Use FILE I/O for reading files
  • Use FILE I/O for writing files
  • Model external Components
Type Of Training:
Online
Execution of Training:
Live Course
Cost:
1800 $ (+ tax)
Date:
Duration:
3 days with 4 hours per day
Location:
Online
Participant Documents Provided:
Work Book with all presentations. Lab Book to be used for exercises.
Course Objectives:
  • Re-visit the basic Verilog Concept
  • Define Verilog Test Fixtures
  • Use FILE I/O for reading files
  • Use FILE I/O for writing files
Type Of Training:
Shorties
Execution of Training:
Live Course
Cost:
99 $ (+ tax)
Date:
Duration:
4 hours
Location:
Online
Participant Documents Provided:
Work Book with all presentations. Lab Book to be used for exercises.
Course Objectives:
  • Re-visit the basic Verilog Concept
  • Define Verilog Test Fixtures
  • Use FILE I/O for reading files
  • Use FILE I/O for writing files
Type Of Training:
Webinar
Execution of Training:
Live Course
Cost:
Free
Date:
Duration:
1 hour
Location:
Online
Participant Documents Provided:
Work Book with all presentations.
Course Objectives:
  • Define Verilog Test Fixtures
  • Generate the Stmuli

A basic knowledge in digital circuit design (gates, multiplexers, flip-flops, memories), are welcome. The theoretical content is supplemented by exercises presented by the trainer and carried out by the participant.

1. VHDL Concept and Design Units

1.1. Design Paradigm

1.2. Libraries and compiled units

1.3. Packages

1.4. Entity

1.5. Architecture

1.6. Configuration

1.7. Test Bench and Simulation

2. Data Types

2.1. Scalar

2.2. Complex Types

2.3. Sub Types and Aliases

2.4. Attributes

3. Naming Conventions and Declarations

4. Statements and Assignments

5. Sequential Statements

5.1. Statements

5.2. Sub Programs

6. Signals

6.1. Declaration

6.2. Signal Assignments inside Processes

6.3. Implicitly Signal Type Resolution and Bus Driver

6.4. Attributes

7. Concurrent Statements

8. Structural Descriptions

8.1. Hierarchical Descriptions

8.2. Use of Packages

8.3. Configurations

8.4. Generics

8.5. Structural Statements

9. Libraries and Packages

9.1. Packages

9.1.1. STD_LOGIC_1164

9.1.2. Unsigned

9.1.3. Fixed Point Package 

9.1.4. Floating Point Package

9.2. Libraries

10. Test Bench

10.1. Introduction to Test Benches

10.2. Types of Test Benches

10.3. Example

11. Labs

11.1. Simple Counter

11.2. Finite State Machines

11.3. UART

11.4. Fixed Point / Floating Point Arithmetic

A basic knowledge in digital circuit design (gates, multiplexers, flip-flops, memories), are welcome. The theoretical content is supplemented by exercises presented by the trainer and carried out by the participant. Each training session is organized as 9.00 a.m. - 11.00 a.m. Days Lecture part 1 11.00 a.m. - 11.15 a.m. 15 minutes break 11.15 a.m. - 1.15 p.m. Days Lecture part 2 Exercises by the participants In order to deepen the theoretical content, the participants receive exercises after each test session that they can carry out independently. The estimated time for completion is appr. 2-3 hours. The results / sample solutions are presented by the trainer the next day. After registration: the participant receives the presentation documents in electronic form (PDF) as well as the workbook for the exercises, the login data and a list of requirements to be done in advanced.

1. VHDL Concept and Design Units

1.1. Design Paradigm

1.2. Libraries and compiled units

1.3. Packages

1.4. Entity

1.5. Architecture

1.6. Configuration

1.7. Test Bench and Simulation

2. Data Types

2.1. Scalar

2.2. Complex Types

2.3. Sub Types and Aliases

2.4. Attributes

3. Naming Conventions and Declarations

4. Statements and Assignments

5. Sequential Statements

5.1. Statements

5.2. Sub Programs

6. Signals

6.1. Declaration

6.2. Signal Assignments inside Processes

6.3. Implicitly Signal Type Resolution and Bus Driver

6.4. Attributes

7. Concurrent Statements

8. Structural Descriptions

8.1. Hierarchical Descriptions

8.2. Use of Packages

8.3. Configurations

8.4. Generics

8.5. Structural Statements

9. Libraries and Packages

9.1. Packages

9.1.1. STD_LOGIC_1164

9.1.2. Unsigned

9.1.3. Fixed Point Package 

9.1.4. Floating Point Package

9.2. Libraries

10. Test Bench

10.1. Introduction to Test Benches

10.2. Types of Test Benches

10.3. Example

11. Labs

11.1. Simple Counter

11.2. Finite State Machines

11.3. UART

11.4. Fixed Point / Floating Point Arithmetic

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