Verilog for Simulation
Verilog Hardware Description Language offers a powerful concept which prohibits typical programming mistakes in the coding phase. Usually, Verilog is used on the register transfer level (RTL) to design digital circuits of any complexity.
Apart from the language constructs for synthesis, Verilog offers a wide range of functionality to describe complex verification models. thus, it is possible verify digital designs from simple gate up to complicated System-on-Chip (SoC) before going to lab tests.
With recourse to already well-known Verilog Language features, this workshop will deepen the knowledge in Verilog and enable the attendee to create simulations with the Verilog testbench concept. The theoretical knowledge will be deepened with selected examples and labs on PC.
A basic knowledge in the Verilog hardware description language, e.g. from Workshop “Intensive Verilog for Synthesis” is desirable. The theoretical content is supplemented by exercises carried out by the participant.
To learn more about Verilog see also our training Verilog for Synthesis.