VHDL for Simulation
VHDL is a strongly typed hardware description language which prohibits typical programming mistakes in the coding phase. Usually, VHDL is used on the register transfer level (RTL) to design digital circuits of any complexity. Apart from the language constructs for synthesis, VHDL offers a wide range of functionality to describe complex verification models. With recourse to already well-known VHDL language features, this LEC2 intensive workshop will deepen the knowledge in VHDL and enable the attendee to create simulations with the VHDL testbench concept.
To learn more about VHDL see also our training VHDL for Synthesis.